(a) Field of the Invention
The present invention relates to a method for forming a capacitive element in which a plurality of minute capacitive elements having a large electrostatic capacitance are formed by making a surface of a bottom electrode to have hemispherical grains (HSGs), more in detail to the method for forming the minute capacitive elements having the large electrostatic capacitance by injecting dopants at a high concentration into the HSGs of the bottom electrode.
(b) Description of the Related Art
A semiconductor device such as a DRAM includes a capacitive element such as a stacked capacitor and a trench capacitor as a component for a memory cell circuit. The capacitive element generally includes a bottom electrode, a dielectric film and a top electrode.
When a stacked capacitive element is conventionally manufactured, the bottom electrode is formed by growing a polysilicon film on a dielectric film overlying a semiconductor substrate, introducing impurities such as phosphorus into the polysilicon film and patterning the polysilicon film by a photolithographic and etching technique. Then, after a dielectric film such as an oxide film and a nitride film is formed on the bottom electrode, the top electrode is formed, similarly to the bottom electrode, to provide the capacitive element.
With the development of miniaturization and high integration of the semiconductor device, the capacitive element employed as the component thereof is also required to be miniaturized. Recently, a capacitive element for securing a large electrostatic capacitance by employing a small electrode has been realized by increasing a surface area of a bottom electrode having HSGs.
A configuration of the capacitive element having the bottom electrode composed of HSGs will be described referring to FIGS. 1A and 1B. The structure of FIG. 1B is different from that of FIG. 1A only in that the bottom electrode 11A in FIG. 1B has no HSGs while the bottom electrode 11 in FIG. 1A has HSGs.
The bottom electrode 11 of the capacitive element is formed on a plug 14 penetrating through an interlayer dielectric film 13 to a silicon substrate 12 as shown in FIG. 1A. The bottom end of the plug 14 is in contact with a region such as a source diffused region 17S formed on the silicon substrate 12. In FIGS. 1A and 1B, numerals 17D and 17G denote a drain diffused layer and a bit line, respectively.
In FIG. 1A, the bottom electrode 11 has on its surface a plenty of HSGs. The respective grains have a mushroom or semispherical convex shape of which a diameter is about between 30 and 70 nm, thereby increasing the surface area of the bottom electrode 11. The surface area of the bottom electrode 11 having the HSG amounts to about twice that of the bottom electrode 11A having no HSGs shown in FIG. 1B.
The bottom electrode having the HSGs is generally is manufactured in accordance with the following process.
A doped amorphous silicon film, for example, a phosphorous (P)-doped amorphous silicon film is formed on a dielectric layer, followed by patterning thereof to form a bottom electrode. Then, the P-doped amorphous silicon film is treated to have the HSGs in accordance with a known process and under known conditions. Then, the bottom electrode having the HSGs is thermally treated at a temperature of 800.degree. C. or more to crystallize the amorphous silicon and to diffuse the phosphorus in the amorphous silicon film into the HSGs to provide the bottom electrode with higher conductivity.
Meanwhile, the thermal treatment temperature of the above capacitive element forming process should be lowered by reasons on structural and circuit designs of the semiconductor device together with the advance of miniaturization and complexity thereof. This is because the components such as transistors mounted together with the capacitive elements on a wafer should be protected from the damage due to exposure to a high temperature during the above thermal treatment
For example, in a 1 G-bit DRAM or a DRAM mounted with a logic circuit, when the thermal treatment of the process of forming the capacitive element is conducted at a temperature of 800.degree. C. or more, impurities in source/drain diffused regions diffuse to shorten a gate length, and impurities (for example, boron) in a gate diffuse to change a threshold voltage of the transistor. in addition, if the wafer having a Ti-silicide film or a Co-silicide film on the surface of the source/drain diffused region or the gate electrode is thermally treated, the silicide film is coagulated to increase the electric resistance. As described above, the thermal treatment at the temperature of 800.degree. C. or more lowers the characteristic of the element such as the transistor, and is hardly conducted reluctantly.
However, the lowering of the thermal treatment temperature below 800.degree. C. reduces a diffusion rate of the phosphorus in the P-doped amorphous silicon film to make difficult the diffusion of the phosphorous through a narrow throat, generally formed at the base of the respective HSGs, into the HSGs. Thus, capacitance reduction due to depletion of the dopant in the HSGs may occur due to the lowering of the diffusion rate.
Then, the capacitance reduction due to the depletion of the dopants in the HSGs will be described referring to FIGS. 2A and 2B. FIG. 2A is a graph exemplifying an ideal C-V characteristic of a capacitive element, and FIG. 2B is a graph exemplifying a curent-voltage characteristic obtained by a thermal treatment for 10 minutes at 800.degree. C. lower than a conventional thermal treatment temperature. In the both graphs, the characteristic of the bottom electrode having the HSGs are compared with that having no HSGs.
The comparison of the graphs of FIGS. 2A and 2B indicates that when the thermal treatment temperature after the formation of the HSGs is low, the resultant capacitance significantly reduces due to depleion of the carriers in the HSGs if an applied voltage (V) of a top electrode is lower than the potential of the bottom electrode. In other words, when the applied voltage of the top electrode becomes higher than the potential of the bottom electrode, the capacitance of the N-type bottom electrode slightly increases because electrons are attracted in the bottom electrode, whereas when the applied voltage becomes lower, the electrons in the bottom electrode are expelled to further proceed the depletion of electrons to lower the capacitance.
The phenomenon concerning the dopant depletion of the HSGs will be further described referring to FIGS. 3A to 3C in which a dense hatching part indicates a higher concentration region of impurities (phosphorous) whereas a non-hatching part indicates a lower concentration region.
The interior of the HSGs is non-doped immediately after the treatment for forming the HSGs as shown in FIG. 3A, and all the region is a depleted region "E" having substantially no dopant. The succeeding high temperature treatment at 800.degree. C. or more makes the phosphorous sufficiently diffuse from the P-doped amorphous silicon film into the HSGs to extinguish the depleted region "E".
However, if the thermal treatment is below 800.degree. C., the diffusion rate of the phosphorus in the silicon film is reduced to make it difficult for the dopants to diffuse through the narrow throat at the bases of the HSGs 15 into the bodies of the HSGs 15. The insufficient diffusion of the phosphorus into the HSGs 15 keeps a most part of the HSGs 15 as a depleted region.
The existence of the depleted region "E" reduces the capacitance due to the above-described reasons when the applied voltage of the top electrode becomes lower.
A phosphorus solid phase diffusion method by employing POCl.sub.3 for suppressing the depletion is described in, for example, JP-A-5(1993)-343614, JP-A-7(1995)-38062 and JP-A-9(1997)-289292.
The method includes to a thermal treatment of a wafer having HSGs at a temperature below 800.degree. C. in a furnace in which the POCl.sub.3 flows. In accordance with the doping of the phosphorus by the solid phase diffusion method, a SiO.sub.2 film 16 having a high concentration of phosphorus is formed on the surface of the HSGs as shown in FIG. 4. It is recited in the publications that the phosphorus in the SiO.sub.2 film 16 diffuses into the interior of the HSGs 15 to form a diffused region "P" of the phosphorus.
In the conventional method of forming a bottom electrode which includes a doping step in accordance with the above described solid phase diffusion, a PSG (Phospho-Silicate Glass) film is formed as the SiO.sub.2 film 16 including the phosphorus by utilizing oxidation of silicon. Since a quality of this type of SiO.sub.2 film 16 is poor and a thickness thereof is thick, the film is not suitable for a capacitive dielectric film. Accordingly, the SiO.sub.2 film 16 is removed by means of hydrofluoric acid after a thermal treatment.
The removal of the SiO.sub.2 film 16 by means of the hydrofluoric acid generates a loss (.DELTA.D) to decrease the particle size of the HSGs to produce the following problems.
A first problem is that the reduction of the surface area of the HSGs hardly increases an electrostatic capacitance as desired.
A second problem is that the HSGs 15 are liable to be dropped by means of reduction of a mechanical strength due to thinning of the base of the HSGs 15 caused by the reduction of the particle size of the HSGs 15.
Therefore, in place of the solid phase diffusion method of the phosphorus, a gas phase diffusion process is attempted in which the bottom electrode having the HSGs is thermally treated at a temperature between 600 and 800.degree. C. in an ambient having a dopant gas which does not react with silicon, for example, in a AsH.sub.3 or PH.sub.3 ambient. The gas phase diffusion process which does not reduce the HSGs in size uses injection of dopants into the HSGs at a high concentration to prevent the reduction of the capacitance due to the depletion.
However, in the attempted process, lesser variation on qualities of wafers, securing of a stable and high amount of doping, and formation of the minute capacitive element having a large and desired electrostatic capacitance are hardly achieved because of the following reasons.
The present inventor has found, during a research for overcoming the problem of hardly elevating a doping amount as desired in the attempted process, that the doping efficiency is low due to a spontaneous oxidation film existing on the surface of the HSGs of the bottom electrode as shown in FIG. 5.
The present inventor has also found that the spontaneous oxidation film is formed in accordance with the following process.
The spontaneous oxidation film is formed by a reaction between the HSGs and oxygen or water which may exist during a waiting time in a stage between the conveyance of the bottom electrode having the HSGs and a start of the doping. The spontaneous oxidation film is also formed by oxygen or water remaining in the furnace, after the formation of the HSGs of the bottom electrode, during subsequent stages, beginning from a cleansing treatment with ammonia water, a mixed liquid consisting of hydrogen peroxide and sulfuric acid and a mixed liquid consisting of hydrogen peroxide and hydrochloric acid, to the start of the doping after the conveyance to the furnace. Thus, the degree of the oxidation film formation depends on the waiting time and the amount of the remaining oxygen.
If the waiting time is smaller and there is substantially no residual oxygen, a specified amount of the dopant can be secured because no spontaneous oxidation film is formed. However, a longer waiting time or a significant amount of residual oxygen forms the oxidation film and the specified amount of the dopant can not be secured. In this manner, the doping amount is largely varies depending on the state of the treatment process and the desired capacitance cannot be obtained.
As a result, the scattering of the doping amount is a main factor of decreasing a yield of manufacturing the semiconductor device having the capacitive element.
In order to overcome this disadvantage, a large-size capacitive element may be employed not to decrease a yield even though a doping amount somewhat varies. However, the cost of the semiconductor device increases because the large-size capacitive element increases a chip area.